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    • 专利摘要:
    In processing systems 120 and 220, signal processors 124 and 224 schedule tasks for execution by one or more command processors 122 and 222 and send signals associated with the job to the command processor when the command processor executes the jobs. do. The current list 150 is maintained in memory by the command processor 122. The current job executed by the command processor causes the command processor to generate a buffered signal associated with the new job to be executed, which causes the command processor to selectively generate a buffered signal associated with the new job. To be stored. Selective storage of buffered signals in the current list depends on the priority level of the current task. If the instruction in the current task that generates the buffered signal is in a predetermined order within the current task, the new task is executed immediately at the end of the current task. When the command processor finishes executing a job associated with a buffered signal, the command processor may optionally (1) issue an exit signal if the job associated with the buffered signal has a predetermined priority level or the current list is empty. Sending to a signal processor; (2) [if the signal processor issues an interrupt to the command processor] sending all remaining work in the current list to the signal processor; (3) Fetch and execute additional tasks into the current list.
    公开号:KR20000064491A
    申请号:KR1019980704692
    申请日:1996-12-19
    公开日:2000-11-06
    发明作者:미카엘 론스트롬
    申请人:에를링 블로메, 타게 뢰브그렌；텔레폰아크티에볼라게트 엘엠 에릭슨；
    IPC主号:
    专利说明:

    Job Scheduling for Command Processors
    A processing system such as Ericsson's APZ 212 20 uses a signal processor for scheduling tasks for execution by the instruction processor, enabling very fast context switching between tasks executed by the instruction processor. The context switching time is usually very fast in a system compared to other systems.
    In such a system, each task has a signal associated with it. The signal contains information that advises the instruction processor about which code block (e.g., in program storage) is executed by the instruction processor in conjunction with the task, and the data used in such execution. When a job is executed by the command processor, a new signal (associated with the new job) is obtained by the signal processor and sent to the command processor. The new signal is obtained by the signal processor from a selected one of the plurality of work buffers of the signal processor, and the new signal is obtained in priority.
    The new task obtained from the signal processor is not entirely related to the old task and therefore uses entirely different data. Moreover, other jobs arrive from external sources (e.g., other processing systems) and, at higher priorities, job interrupt execution of older jobs before older jobs exits.
    Therefore, in the permanent processing system, the code and data change the context very often. It means that the context is lost and therefore often nothing is obtained by using fast memory (eg cache memory) to preserve the context. In such a system, only the context preservation used saves data in registers, and it can only be done during one task execution.
    In more detail in consideration of such a system, FIG. 1 shows a central processing unit 20 portion, in particular a command processor unit (IP) 22; A signal processing (SP) unit 24; Program storage (PS) 26; Data and reference storage (DRS) 28; A plurality of region handler bus handlers (RPHs) 30 1,... N ; An " other " processor bus handler (IPH) 31; The holding unit (MAU) 32 is shown. Each command processor 22, signal processor 24, IPHB 31, and RPHs 30 are independent processors. The command processor 22 executes a job, and each job corresponds to a command block stored in the program storage (PS) 26. The signal processor 24 serves as a scheduler for the job for the command processor 22. In connection with such scheduling, the signal processor 24 receives, for example, a "signal" from the outside or from the command processor 22 for each task. The signal is command telling and the signal contains data used in the block execution for execution in a particular portion of the command block. The signal processor 24 analyzes and prepares the incoming signal and assigns priority to the signal before sending it to the command processor 22. References to data and reference storage 28 include information describing signals, blocks, and variables in the system.
    In some configurations, the central processing system 20 of FIG. 1 may include two command processors 22, two processors 24, one or other processor bus handlers (IPHs) 31, and additional multiple regions. Processor bus handler 30, all of which are connected to the mirror image of FIG. 1 via MAU 32 and buses 34 and 36. FIG. In such a configuration, each command processor 22 has its own program store 26 and its own data and reference store 28.
    Area handler bus handlers (RPHs) 30 1,... N are connected to an area handler, not illustrated by the corresponding area handler bus. Similarly, one or more other processor bus handlers 31 may also be provided to connect to the appropriate bus 39. As command processor 22 is included when executing application software stored in program store 26, not only signal processor 24, but also area processor bus handlers (RPHs) 30 1, ... n and other processor bus handlers. All serve to reduce the load on command processor 22.
    2 shows in more detail the command processor 22, the signal processor 24, the other processor bus handlers 31, and area processor bus handlers (RPHs) 30 1,... N of the central processing system 20. And the interaction between them. In particular, FIG. 2 shows a signal processor 24 having a job scheduler 40 and also a plurality of job buffers 42A-42D known as buffers A-D, respectively.
    In the central processing system 20, when the command processor 22 completes the task (as indicated by sending an exit signal to the signal processor 24), the signal processor 24 has the highest priority and is not yet empty. The next job is searched to be executed from one of the unbuffered buffers 42A to 42D. The signal processor 24 also sends a signal to the command processor 22 associated with the task to be executed next. The receipt of such a signal prompts the command processor 22 to begin its execution in a new block of code specified by the signal.
    From time to time, the command executed by the command processor 22 prompts the command processor 22 itself to generate a new signal. The signals generated by the command processor are of various forms: combined signals, RP signals, other command processor signals, and buffered signals. The combined signal is very similar to a subroutine call, and consequently causes the command processor 22 to immediately execute the combined signal and return to execute the task in which the combined signal is generated.
    The RP signal and other command processor signals generated by the command processor 22 are signals associated with the work executed by the area processor (in the case of the RP signal) or another command processor (in the case of the IP signal). The RP signal or other IP signal is received by the signal processor 24 and sent to the appropriate one of the area processor bus handlers 30 (in the case of other IP signals) or to another processor bus handler 31 (in the case of RP signals). Is sent.
    Except for the combined signal generated by the command processor 22, the IP-generated signal is referred to as a "buffered signal". According to the prior art, the buffered signal is sent to the signal processor 24 (as indicated by line 54 in FIG. 2). Execution by command processor 22 continues in the block and command processor 22 is currently executing. Upon receipt of the buffered signal emitted from the command processor 22, the signal processor 24 obtains one of two potential operations in accordance with the priority level of the received and buffered signal. In particular, if the priority level of the received and buffered signal is greater than the priority level of the task currently executed by the command processor 22 (ie, generating the buffered signal), then the signal processor 24 will interrupt. Send to command processor 22 to interrupt the current job (as indicated by line 56 in FIG. 2). Otherwise, the signal processor 24 puts the buffered signal into one of the job buffers 42A to 42D having the same priority as the buffered signal as the last job. In such a manner, the buffered signal is executed as any other signal of the same priority as the buffered signal (as indicated by line 58 in FIG. 2).
    Therefore, as mentioned above, in the prior art, the exit command is executed by the command processor 22 at the end of the job, and the command processor 22 always checks the signal processor 24 for scheduling of the next job. In such scheduling, signal processor 24 fetches the next job in priority from job buffers 42A-42D. However, setting up the prior art scheduling scheme, the fetched job is not entirely related to the previous job. Similar to unrelated tasks, other data is usually used. Also, when a job arrives with higher priority, they interrupt the job execution before the exit instruction arrives.
    The central processing system 20 has a number of implementations, including as a control system for a telephone switching system, for example. As mentioned above, one example of such an embodiment is described in "APZ 21220--The New High end Processor for AXE 10", Ericsson Review, No. 1, 1995, pp. 5-12, described by Egeland, Terje, APZ 21220 control system for Ericsson AXE 10.
    In a central processing system, there is a need for a method that often does not change context, thereby effectively using very fast memory, such as cache memory. Another desired improvement is that the signal processor alleviates the task.
    The present invention relates to the scheduling of jobs for execution by the command processor included in the central processing system.
    The foregoing and other objects, features, and advantages of the present invention will become apparent from the following more specific description of the preferred embodiments, as illustrated in the accompanying drawings, in which reference characters refer to the same parts throughout the several views. The drawings need not be focused on being drawn instead of being positioned when illustrating the principles of the invention.
    1 is a schematic diagram of at least a portion of a central processing unit;
    2 is a schematic diagram illustrating various components provided for a central processing system in accordance with the prior art;
    3 is a schematic diagram illustrating various components provided for a central processing system in accordance with one embodiment of the present invention.
    4 is a schematic diagram illustrating one example of a configuration of a command processor provided for the central processing system of FIG.
    5 is a schematic diagram illustrating various components provided for a central processing system based on a number of instructions in accordance with another embodiment of the present invention.
    FIG. 6 is a schematic diagram showing events generated by a signal processor of the central processing system of FIG. 3 and events generated. FIG.
    FIG. 7 is a schematic diagram illustrating events generated and states caused by the command processor of the central processing system of FIG. 3; FIG.
    8 (1) is a flowchart showing the steps executed by the signal processor when generating an exit signal from the command processor.
    8 (2) is a flowchart showing the steps performed by the signal processor when generating a (non-exit) signal from the command processor.
    8 (3) is a flow chart showing the steps executed by the signal processor when generating a timeout event.
    Fig. 8 (4) is a flowchart showing the steps executed by the signal processor when generating a signal from the area processor RP or another command processor.
    9 (1) to 9 (3) are schematic diagrams showing the steps executed by the command processor performing each of the actions A (SP) 1 to A (SP) 3.
    Fig. 9 (4) is a flowchart showing the steps executed by the command processor performing the action A (SP) 4;
    9 (5) to 9 (10) are schematic diagrams showing steps executed by a command processor for performing each of actions A (SP) 5 to A (SP) 10.
    Fig. 9 (11) is a flowchart showing the steps executed by the command processor performing the action A (SP) 11;
    10 is a schematic diagram of a signal format used by the present invention.
    Signal scheduling for execution by the command processor is basically performed by the signal processor. According to the invention, the signal processor has a unique scheduling technique and the command processor performs some of its scheduling without interrupting the signal processor (using the "current list" memory).
    The signal processor allocates the signal to be executed in one of four buffers according to the signal's assigned priority, for example scheduling buffer (A), scheduling buffer (B), scheduling buffer (C), or scheduling buffer (D). . In general, when the command processor needs a new signal for execution from the signal processor (as occurs when receiving an exit signal from the command processor), the signal is old (oldest) and priority level (i.e. levels A, B). Are fetched from the buffers A to D according to C, or D). (As used herein, the designation of the "highest" priority level does not take into account the trace level).
    If the priority level of a fetched job is a "C" priority level or a "D" priority level, the signal processor determines if jobs of similar priority levels are currently interrupted, and then dispatches the fetched jobs to the appropriate Resumes execution of the interrupted task while sending back. Also, the command processor may execute a level D signal at a time when the signal processor receives a higher priority signal (e.g., from the command processor, from the area processor, or from an "other" command processor). Execution of the level D signal is interrupted immediately.
    Execution of the signal by the command processor IP generates a new signal. The signal generated by such a command processor is typically generated just before the exit command of the signal. The signal generated by such a command processor may be a combined signal or a buffered signal (all of which are executed by the command processor) or a signal directed to another processor (area processor or "other" command processor). The combined signal is very similar to the subroutine call, and consequently causes the command processor to immediately execute the combined signal and return to execute the signal from which the combined signal is generated.
    When a buffered signal is generated by the command processor, the command processor puts the buffered signal in a particular register or queue known as the "current list." If the buffered signal is generated just before the exit of the currently executing job, then only the lowest priority level is set, and if no interrupt is set, the job associated with the buffered signal is executed on exit from the job where the buffered signal is generated.
    Subsequently, when the command processor exits a job executed as a result of the generation of the buffered signal, the command processor takes one of several alternative steps depending on the priority level of the buffered signal and whether an interrupt is set. Can be done. The first alternative involves getting the first (next) task from the current list and doing the same. The second alternative step includes returning scheduling control to the signal processor as occurs when the buffered signal is at the lowest priority level. A third alternative step involves moving the entire contents of the current list to the signal processor as occurs when an interrupt occurs. In conjunction with the first alternative, a continuous task on the current list can be executed continuously as if the task on the current list exits.
    The task associated with the buffered signal is executed immediately after having caused the task of generating the buffered signal to be triggered immediately before the set instruction type (eg exit command). Therefore, the instructions that generate the buffered signals must be in a predetermined order within the task to have the buffered signals executed immediately upon completion of the task. Otherwise, the task associated with the buffered signal will remain in the current list, run continuously with the task associated with the other buffered signal, or even move to the signal processor.
    Each time a task execution is interrupted by the command processor, the entire contents of the current list are moved to the signal processor. The signal processor puts the signal from the current list into the appropriate one of the buffers according to the priority level of the moved signal.
    The signal processor has the ability to send signals to the current list. When a signal processor sends a signal to a command processor for execution, the signal processor searches the buffer and moves another signal in its buffer (s) with the same thread identification as the signal moved to the command processor to the current list. Let's do it. Signals that the thread ID of an externally generated signal (e.g., received via either the area handler bus handler or the handler bus handler) will not be interrupted or set by the CurrentThreadID processed by the command processor or consequently the interrupt flag. When the processor decides, a similar posting of the signal occurs on the current list.
    The central processing system 120 of FIG. 3 includes a command processor unit (IP) 122; A signal processing (SP) unit 124; Program storage (PS) 126; Data and reference storage (DRS) 128; A plurality of region handler bus handlers (RPHs) 130 1,... N ; "Other" handler bus handler (IPH) 131. Unless otherwise explicitly or implicitly mentioned, similarly named elements of system 120 are the same as those mentioned above of system 20 of FIG. 2. The difference between system 120 and system 20 is the current list memory 150 that is stored by the command processor 122 in a series of registers of the access command processor 122. The signal processor 124 also has a timer 141.
    The central processing system 120 of FIG. 3 is realized in the illustrated embodiment using a Sun Ultra 2 workstation having two processors operating with shared memory. Those skilled in the art understand how to send signals in two processing periods through a shared memory technology.
    The command processor 122 and the signal processor 124 operate in a different way than that done to the corresponding processor of the prior art. In particular, as will be discussed in more detail below, the command processor 122 selectively stores the buffered signals it generates on the current list 150, bypassing the signal processor 124 and providing good context protection. . The signal processor 124 allows one or more buffered signals to be executed in the current list 150 while the time limit is not exceeded. Also, when signal processor 124 has a higher priority level job, signal processor 124 always interrupts the " D " priority level job by command processor 122 in the middle of job execution. The signal processor 124 causes the "A" priority level task to also interrupt other tasks upon signal transmission.
    4 shows one configuration of the command processor 122. In the configuration of FIG. 4, the command processor 122 includes a central processing unit (CPU) 160; Register memory 162; Fast memory 164; Memory access / interface 166; A plurality of cache memories 168A to 168C; A plurality of memory cards 170A to 170G; It has a memory bus 172 that connects memory access / interface 166 to card 170. In the configuration shown in FIG. 4, cache memory 168B has 16 byte access and cache memory 168C has 4 byte access. The cards 170A to 170F are DRAM main memory cards. The card 170G is a direct memory access (DMA) card connected by an IOB bus to a peripheral device such as a disk drive controller, and it is possible to use another memory device such as a disk.
    In the command processor configuration of FIG. 4, fast memory 164 is used to access very frequently used variables, such as data structures that lock and maintain tracks of disk buffers. The assignment of variables to specific memory types can be done through the compiler or by the designer. Cache memories 168A-168C have varying line sizes to provide flexibility. The variable to be cached can also be specified as a block parameter or variable form.
    10 illustrates a signal format used by one embodiment of the present invention. As shown in Fig. 10, the signal includes a first field " ThreadID " representing a thread to which the signal belongs; A second field "JobLevel" indicating the priority of the signal; A third field " FORMAT " represented by the number of data items in the last field of the signal; A fourth field "SignalNumber" indicating the number of sequences of the signal; A sixth field "RecBlock" that is the number of blocks to receive; A seventh field "SendBlock" which is the number of blocks to send; An eighth field "Forlopp Id" which is an identification used for reliability purposes; A ninth field "RegPRO" containing a first data value; And a tenth field "DataList" containing one or more other data values (equivalent to 24).
    A thread contains a set of tasks that need to be executed in response to a message received from an external system (eg, from a region handler or "other" command processor). In a thread, several tasks can run concurrently, and communication with the external system can occur as part of the thread.
    action
    The events recognized by the signal processor 124 and the actions taken are shown in FIG. 6. The events recognized by the command processor 122 and the actions taken are shown in FIG. 7. The event recognized by the signal processor is indicated as an identifier of form "E (SP) x"; The event acknowledged by command processor 122 is indicated as an identifier of form "E (IP) x". The action obtained by the signal processor 124 is represented as an identifier of the form "A (SP) x"; The action obtained by the command processor 122 is displayed as an identifier of the form "A (IP) x". In all such identifiers, the "x" is referred to as the event or action number.
    As shown in Fig. 6, the signal processor 124 has three states: an idle state; Operating state; And a queued state. The state change is illustrated by bold face lines in FIG. 6. 6 shows that the signal processor 124 generates four "SP" events at specific events (E (SP) 1 to E (SP) 4). Signal processor 124 may be in any of three states when it generates an SP event. For this reason, it is shown that each SP event of FIG. 6 enters each state (in dashed lines).
    For each SP event in FIG. 6, the signal processor 124 responds to the corresponding action. As used herein, an "action" may comprise one or more steps, which steps may alternatively or continuously be executed. The actions performed by the signal processor 124 and the steps of configuring each action are illustrated in each of FIGS. 8 (1) to 8 (4). In time, the steps performed along the action depend on the "state" of the signal processor 124.
    As shown in Fig. 7, the command processor 122 has three states: an idle state; Operating state; And a combined / operational state. Since each state is independent, similarly named states of the command processor 122 and the signal processor 124 are not confused. As in FIG. 6, the state change is illustrated by boldface lines in FIG. 7. 7 shows that the signal processor 124 generates eleven "IP" events at specific events (E (SP) 1 to E (SP) 11). Some of these IP events, taking IP events E (IP) 1, E (IP) 3, and E (IP) 9 as examples, occur in connection with the action performed by the signal processor 124.
    The signal processor 124 and the command processor 122 are correlated such that certain IP events occur only when the command processor 124 is one or more of its states. In this relationship, the action performed by command processor 122 is shown in a circle showing the state in which the action occurs. The state in which the IP event may occur is indicated by the dotted line in FIG. The steps involved as IP actions E (IP) 1 through E (IP) 11 are shown in more detail in each of FIGS. 9 (1) -9 (11). As mentioned above, as understood with respect to Figs. 9 (1) -9 (11), various actions performed by the command processor 122 are performed by the SP events E (SP) 1-E (SP) 2 shown in Fig.6. Make.
    A. Signal Processor Operation
    The signal processor 124 operates in conjunction with the timer 141 (see FIG. 3). When loading with a set time value (for example, the value "X" or "Y"), the timer 141 notifies the signal processor 124 when the time interval corresponding to the time value expires. Expiry of a time value, for example, notification by the timer 141, generates a time-out event described in more detail with reference to FIG. 8 (3) (event E (SP) 3). The timeout event allows the signal processor 124 to know if the action of the command processor 122 takes more time. In this relationship, the timer 141 at initialization of a predetermined operation (e.g., transmitting a new signal from the buffer 142 of the execution signal processor 124 by the command processor 122) has a value of "X". (For example, 1 ms). If the timeout occurs without a timer 141 set to a value of " X ", then the signal processor 124 may flag flag SP_ to recognize that the instruction processor 122 executes the same thread ID for one time interval. Set the interrupt. The timer 141 is loaded with the second time value "Y" (eg 3 ms). The obtained action generates a second time end after the expiration of the time value "Y" and depends on the priority level of the task to be executed. If the task being executed is at the "C" or "D" priority level, the task to execute is interrupted. If the task being executed is an "A" or "B" priority level, an error condition is acknowledged and a KILL signal is generated.
    The action performed by the signal processor 124 upon receipt of the SP event is described as follows.
    (1) reception of non-outlet signals by the SP
    In connection with job execution, command processor 122 generates a non-exit signal and assigns a priority level to the generated signal. In the case where such a signal is transmitted to the signal processor 124, the signal processor 124 becomes an event E (SP) 2 as shown in FIG. Upon receipt of event E (SP) 2, signal processor 124 performs action A (SP) 2, the steps of which are illustrated in FIG. 8 (2).
    In each step 8 (2)-1 and 8 (2)-2, the signal processor 124 identifies whether the command processor 122 is directed to either the area processor or the " other " command processor. If the signal received from the command processor 122 is directed to one of the area processors, then at step 8 (2) -3 the signal is sent to the appropriate area processor bus handler 130. If the signal received from the command processor 122 is directed to one of the "other" command processors, then at step 8 (2) -4 the signal is sent to the "other" command processor bus handler 131.
    If the non-exit signal obtained from the command processor 122 is not directed externally, the priority level of the signal currently executed by the command processor 122 is checked in step 8 (2) -5. If the priority level of the currently executing signal excludes the "D" level, then at step 8 (2) -6 the received signal is finally placed in the appropriate working buffers 42A-42D according to its priority. . Otherwise, if the priority level of the currently executing signal is the "D" level, steps 8 (2) -7 are executed. In step 8 (2) -7, the switch time-out is set to an "X" value; The flag task_interrupted_level D is set to be active (to indicate that the task of the priority level D is interrupted); The current ("D" level) job execution is interrupted. Command processor 122 sees the job interrupt as event E (IP) 8 and responds with action A (IP) 8 as described in FIG. 9 (8). Upon completion of steps 8 (2) -3, 8 (2) -4, 8 (2) -6, or 8 (2) -7, action A (SP) 2 is a symbol 8 (2). Exit as indicated by -8).
    (2) Reception of exit signal by SP
    Signal processor 124 receiving an exit signal from command processor 122 (event E (SP) 1) triggers action A (SP) 1, the steps of which are shown in FIG. 8 (1). The exit signal is received from the command processor 122, so action A (SP) 1 is triggered at an instance of the command processor 122 completing the execution of a task that does not appear from the generation of the buffered signal. Alternatively, the exit signal is received when the command processor 122 completes the task or sequence of tasks appearing from the buffered signal (steps 9 (4) -6, 9 (4)-of FIG. 9 (4)-). 9, and 9 (4) -4); Step 9 (7) -3 in Fig. 9 (7); See step 9 (3) -3 of FIG. 9 (3)).
    Upon receipt of the exit signal from the command processor 122 [Event E (SP) 1], the signal processor 124 fetches the first job at the highest priority from the non-empty buffers 142A to 142D [step 8 (1 )-One]. In step 8 (1) -2, the signal processor 122 clears various flags (error_timeout and SP_interrupt) and sets the switch time_end to the value "X". In steps 8 (1) -3 and 8 (1) -4, the priority level of the job fetched in step 8 (1) -1 has a priority level of " C " 1) -3) or " D " (step 8 (1) -4).
    If the fetched job has a priority level "C", then at step 8 (1) -5 the flag job_interrupted_level [C] is activated, i.e. of priority level C. Reference is made to determine if execution by the command processor 122 of another task is already interrupted by the signal processor. If the determination is final in step 9 (1) -5, step 8 (1) -6 is executed. In step 8 (6) -1, the job fetched in step 8 (1) -1 is placed back into the buffer to be fetched; The flag task_interrupted_level C is set not to be active (because the previously interrupted level "C" task is currently executed and therefore not interrupted); The flag activation_priority is set to "C" (to reset the priority level of a previously interrupted job); The interrupted task is resumed. Resumption of job execution interrupted by the signal processor 124 generates the IP event E (IP) 2, which is understood with reference to FIG. 9 (2). Action A (SP) 1 ends (as indicated by symbol 8 (1) -9).
    The fetched job has a priority level of "C", but the flag job_interrupted_level [C] is not active (that is, if a job of priority "C" is not currently interrupted), then step 8 (1 ) -7 and 8 (1) -8) are executed. In step 8 (1) -7, the flag activation_priority is set to be the priority of the job fetched in step 8 (1) -1; A signal associated with the fetched job is sent to the command processor 122 as an IP event E (IP) 1 (see FIG. 9 (1)); CurrentThreadID is set to the thread ID of the fetched job. In step 8 (1) -8, the thread IDs of all jobs in the job buffer of priority level "C" or higher are checked and the thread ID of the job is equal to the CurrentThreadID (that is, the thread ID of the fetched job). If so, a signal associated with each task is sent from the command processor 122 to the current list 150. In return, IP event E (IP) 11 is generated for each job in the job buffer (level "C" or higher) with a thread ID equal to CurrentThreadID. The action obtained by the command processor 122 in response to the IP event E (IP) 11 is described with reference to Fig. 9 (11). Action A (SP) 1 ends (as indicated by symbol 8 (1) -9).
    If the fetched job has a priority level "D" (as determined in step 8 (1) -4), the flag job_interrupted_level [C] and job_ in step 8 (1) -10). Interrupted level [C] is taken into account to determine if execution by command processor 122 of a job of priority level "C" or "D" is currently interrupted by signal processor 124. If the check is determinate in step 8 (1) -10 (i.e. any flag is activated), the job fetched in step 8 (1) -1 is placed back in the buffer [step 8 (1)]. Additional checks are carried out in step 8 (1) -12. In particular, in step 8 (1) -12, an additional discrimination is made to see if the flag task_interrupted_level [C] is activated. If the result of step 8 (1) -12 is deterministic, then at step 8 (1) -13 the flag job_interrupted_level [C] is set not to be activated and the flag activation_priority is "C". Assigned by value. If the result of step 8 (1) -12 is negative, in step 8 (1) -14 the flag operation_interrupted_level [D] is set not to activate and the flag activation_priority is "D". Assigned by value. Upon completion of any of steps 8 (1) -13 and 8 (1) -14, in step 8 (10-15) the signal processor 124 generates an IP event (E) that occurs to the command processor 122. It is instructed to resume execution of the interrupted job of the highest priority by (IP) 2) Then action A (SP) 1 ends as indicated by the symbol 8 (1) -16.
    If it is determined in step 8 (1) -10 that the flag job_interrupted level [C] or job_interrupted level [D] is activated, steps 8 (1) -17 and 8 (1) -18) is executed prior to the end of the action A (SP) 1. In steps 8 (1) -18, the flag activation_priority is set to be the priority of the job fetched in step 8 (1) -1; CurrentThreadID is set to the thread ID of the fetched job; The signal associated with the fetched job is sent to the command processor 122 as an IP event E (IP) 1 in a similar manner to steps 8 (1) -7 (see Fig. 9 (1)). In steps 8 (1) -18, the threads (IDs) of all jobs in the job buffer (with a "C" or higher priority level) are examined and the thread IDs of the job are CurrentThreadIDs (ie, fetches). If it is equal to the number of threads (ID) of the jobs that have been processed, a signal associated with each job is sent from the command processor 122 to the current list 150. In other words, an IP event (E (IP) 11) is generated for each job in the job buffer with a thread ID equal to CurrentThreadID. As indicated previously, the action obtained by command processor 122 in response to IP event E (IP) 11 is described with reference to FIG.
    If the fetched job has a priority level except "C" or "D", steps 8 (1) -19 and 8 (1) -20 are executed prior to the end of action A (SP) 1. do. Steps 8 (1) -19 and 8 (1) -20 are similar to steps 8 (1) -17 and 8 (1) -18) and are essentially sent to the current list 150 of the command processor. End all work on the buffer with a thread ID similar to CurrentThreadID. The end of action A (SP) 1 is indicated by symbols 8 (1) -21.
    (3) Signal reception from RP or others by SP
    Just as signal processor 124 can send signals to region processor bus handler 30 and the " other " command processor bus handler 31, signal processor 124 is configured for event E (SP) 4 in FIG. As indicated by this, you can receive externally generated signals from the handler. Upon reception of the externally generated signal, action A (SP) 4 is performed. The step of action A (SP) 4 is illustrated in FIG. 8 (4).
    In action A (SP) 4, if the externally generated signal does not contain a thread ID (as determined in step 8 (4) -1), the signal processor 124 assigns a thread ID. [Step 8 (4) -2]. For example, the signal processor 124 may assign a thread ID that is incremented each time a new thread ID is assigned by concatenating the processor ID and the internal counter.
    In steps 8 (4) -3 and 8 (4) -4, the signal processor 124 checks the priority level of the externally generated signal. If the state of either step 8 (4) -3 or step 8 (4) -4 is not satisfied, the thread ID state of step 8 (4) -5 is checked. The thread ID status of step 8 (4) -5 is checked. If the thread ID status of step 8 (4) -5 is not satisfied, step 8 (4) -6 is executed.
    In step A (SP) 4-3, if the priority level of the externally generated signal is greater than the priority level of the job currently executed by the command processor 122, it is executed by the command processor 122. The task to be has the lowest ("D") level priority, and signal processor 124 performs steps 8 (4) -7. In step 8 (4) -7, the signal processor 124 sets the switch timeout to the value "X"; Set to activate the flag task_interrupted_level [D] (to indicate that the task at the priority level "D" is interrupted); Send an interrupt to the command processor 122. The command processor 122 views the interrupt as an IP event E (IP) 8, and the response understood to the action A (SP) 8 is described in FIG. 9 (8).
    In step 8 (4) -4, the priority level of the externally generated signal is the highest level (e.g., "A" level priority) and the priority of the job currently executed by the command processor 122. If greater than the rank level, then at step 8 (4) -8 the signal processor 124 sets a flag SP_interrupt (which causes the command processor 122 to execute a new signal at the end of the currently executed job). Also in step 8 (4) -7, the signal processor 124 sets the switch time-out to " Y ".
    Assuming that the externally generated signal does not result in interruption or setting the flag SP_interruption, then at step 8 (SP) 4-5 the signal processor 124 nevertheless causes the externally generated signal Whether the thread ID (received via the area handler bus handler 30 or the handler bus handler 31) is the CurrentThreadID processed by the command handler 122 and the priority level of the externally generated signal Determine if greater than D-level. If so, the externally generated signal in step 8 (4) -9 is sent to command processor 122 to enter the current list 150. Upon receiving a signal (event E (IP) 9), the command processor 122 puts the externally generated signal into the current list 150 as the last entry (see Fig. 9 (9)).
    If none of steps 8 (4) -3 to 8 (4) -5 are performed, then at step 8 (4) -6 the signal processor 124 may have a priority level of the externally generated signal. In response, an externally generated signal is put into a suitable one of the work buffers 142A to 142D. Upon completion of any of steps 8 (4) -7,8 (4) -8, 8 (4) -9, or 8 (4) -6, action A (SP) 4 is a symbol 8 (4). End as shown in 4) -10).
    (4) timeout for SP
    The timer 41 may time out when the value stored for switch time-out is clocked down to zero by the timer 41. When the timer 141 times out, the signal processor 124 may know the time out as an event E (SP) 3 (see FIG. 6), and the action A (SP) 3 and in particular FIG. 8 (3). Perform the steps shown in). At the end of the time, the signal processor 124 first checks in step 8 (3) -1 whether the flag SP_interrupt is set. If the flag is not set, in step 8 (3) -2 the timer 141 (time-end) is set to a value of " Y " and before the action A (SP) 3 ends (symbol 8 ( As indicated by 3) -3)), the flag SP_interrupt is set. If the flag is not set, step 8 (3) -4 is executed next.
    In step 8 (3) -4, the flag SP_interrupt is cleared. Then, in step 8 (3) -5 it is determined whether the job has a priority level of "C" or "D". If the determination is deterministic in step 8 (3) -5, then steps 8 (3) -6, 8 (3) -7, and 8 (3) -8 are determined by the action A (SP) 3. It runs continuously before exiting. In step 8 (3) -6, the signal processor 124 fetches the first (oldest) job from the non-empty one of the highest priority buffers 142A-142D. Then, in step 8 (3) -7, the flag task_interrupted_level (activation_priority) is set to be activated. In other words, the signal processor 124 causes the interruption of the current running task (with the priority level "Activation_Priority") to time out, so that the flag task_interrupted level is the priority of the interrupted task. Note that it should be set to the rank level In step 8 (3) -8, the job currently executed by command processor 122 is interrupted (and a timeout occurs during its execution). Such interruption is seen by the command processor 122 as an IP event E (IP) 8, and the response to it is understood in connection with the action A (IP) 8 as described in Fig. 9 (8).
    If the determination in step 8 (3) -5 is negative, i.e., the priority level of the job currently executed by the command processor 122 is higher than the "C" level, then in step 8 (3) -10 Signal kill _ signal is sent to the command processor 122. The command processor views the signal KILL signal as an IP event E (IP) 3 and generates a response action A (IP) 3 as shown in Fig. 9 (3). At the end of steps 8 (3) -8 and 8 (3) -10, action A (SP) 3 ends as indicated by symbol 8 (3) -3.
    B. Command Processor Operation
    As mentioned previously, as shown in FIG. 7, the command processor 122 may generate a signal in the course of executing tasks in various states. Such IP-generated signals include a signal directed at a region processor or other command processor, combined signals. An event generated by the IP-generated signal is shown in FIG. 7 and corresponds to an event E (IP) 11 corresponding to the generation of the buffered signal; An event (E (IP) 10) corresponding to the generation of the combined signal or the urgent signal; Event (E (IP) 6) corresponding to the generation of a signal for the area processor or " other " The urgent signal is immediately executed by the command processor 122 without considering the signal processor 124, and includes a command processor 122 that changes to a new block and starts execution at that new block. Therefore, unlike a combined signal, an urgent signal means an exit without returning to the calling block.
    The action performed by the command processor 122 in response to the IP event is as follows.
    (1) IP reception signal from SP
    In the idle state, the command processor 122 performs the action A (IP) 1 shown in Fig. 9 (1). In particular, in step 9 (1) -1, command processor 122 changes from a rest state to an operating state (see FIG. 7). Then, in step 9 (1) -2, the instruction processor 122 changes to a new block in its associated program store 126 and starts execution at that new block.
    (2) Interrupted IP Execution
    Upon receipt of the interrupt (event E (IP) 8), the instruction processor 122 obtains the action A (IP) 8 shown in Fig. 9 (8). In step 9 (8) -1, the command processor 122 stores the context. That is, the instruction processor stores a block that is interrupted upon interruption (eg, in register memory 162), its program counter, and the contents of its register. Then, in step 9 (8) -2, the command processor 122 sends a signal to the signal processor 122 for each job stored in the current list 150 to send the contents of the current list 150. Effectively move to the signal processor 124. Thereafter, in step 9 (8) -3, the instruction processor 122 changes to the new priority level of the interrupting signal and executes the task associated with the interrupting signal.
    (3) IP to resume interrupted operation
    When command processor 122 resumes execution of the interrupted task, event E (IP) 2 is generated. The action A (SP) 2 obtained in response to the event E (IP) 2 is shown in FIG. 9 (2). In step 9 (2) -1, instruction processor 122 returns the context of the interrupted task (from register memory 162, as understood above).
    Then, in step 9 (2) -2, the command processor 122 changes to the priority level of the returned task and restarts execution of the signal associated with the returned task.
    (4) IP sending signal to RP or other IP
    Event E (IP) 6 occurs when the code executed by command processor 122 requires the generation of a signal directed to an area processor or " other " command processor. The action obtained by the command processor 122 in response to the IP event E (IP) 6 is shown in FIG. 9 (6). In action A (IP) 6, command processor 122 merely sends such a generated signal to signal processor 124 and the currently executing block (e.g., a region processor or " other " Execution continues in the generated block).
    (5) IP sending combined or urgent signals
    When the code executed by the command processor 122 requires the combined signal or the urgent signal [Event E (IP) 10], the command processor 122 immediately sets the state to the combined state (Fig. 7 and Fig.). Step 9 (10) (see 9 (10) -1). Thereafter, in step 9 (10) -2, the instruction processor 122 stores the calling block (i.e., the block of instructions for which a combined or urgent signal is generated) and returns the return address for the calling block on top of the stack. Put it in. In step 9 (10) -3, the instruction processor 122 changes to a new block required for execution by a combined or urgent signal and starts execution at the beginning of that new block.
    (6) IP exiting combined or urgent signal
    Event E (IP) 5 occurs when command processor 122 is coupled or issues an exit command of an urgent signal. Upon occurrence of event E (IP) 5, action A (IP) 5 is obtained as described in FIG. 9 (5). In step 9 (5) -1, the instruction processor 122 returns the calling block (i.e., the block in which the combined or urgent signal is generated) and the next instruction for execution in the calling block from the stack of the instruction processor 122. Returns the address of. In step 9 (5) -2 the instruction processor 122 checks whether the flag " last combined signal_return " is set to indicate that the stack is empty, and if so, checks the state of the instruction processor 122. Set to working state. Then, in step 9 (5) -3, the instruction processor 122 resumes execution of the block calling in the instruction specified by the stack address.
    (7) IP sending buffered signal
    When the command executed by the command processor 122 invokes the generation of the buffered signal [event (E (IP) 11), the command processor 122 is executed by the action A (IP) shown in Fig. 9 (11). 11) The priority level of the task currently executing in step 9 (11) -1 is evaluated to determine if it is the lowest ("D") level. At 2), the buffered signal is sent to signal processor 124 as event E (SP) 2 (see FIG. 6) and as action A (IP) 11 ends (symbol 9 (11)). Execution continues in the buffer-signal generating block (as indicated by -4) (as indicated by step 9 (11) -3).
    If the priority level of the currently executing job has a priority level other than the lowest priority level, it is determined in step 9 (11) -5 whether the next command executed is an exit command and whether the flag SP_interrupt is not set. do. If all of the conditions in step 9 (11) -5 are deterministic, the exit command (as indicated by step 9 (11) -6) is combined with the command processor 122 as part of the signal transmission command and the command processor Performed by 122. Otherwise, if either of the conditions of step 9 (11) -5 is negative, the command processor 122 puts the job associated with the buffered signal as the last job on the current list (step 9 (11)). Upon completion of any of steps 9 (11) -6 or 9 (11) -7, action A (IP) 11 ends as indicated by symbol 9 (11) -4. do.
    (8) IP to exit buffered signal
    As the command processor 122 executes a task associated with the buffered signal, the command processor 122 eventually issues an exit instruction (event E (IP) 4). At this time, the command processor 122 performs the action A (SP) 4 depicted in Fig. 9 (4), " buffered signal " includes the signal generated by the command processor 122 in the above-mentioned manner. In addition, it includes all of the signals scheduled by the signal processor 124 with respect to the command processor 122.
    In conjunction with action A (IP) 4, command processor 122 performs the check indicated by step 9 (4) -3, and if all such checks are negative, action A (IP) 4 Step 9 (4) -4 is executed before completion (as indicated by symbol 9 (4) -5).
    In step 9 (4) -1, the command processor 122 determines whether the job being executed is at the lowest priority level ("D") level. If so, in step 9 (4) -6, the instruction processor 122 sets the state to the idle state and then sends an exit signal to the signal processor 124 and is handled by the signal processor 124 (Fig. 6). See event (E (SP) 1)). The remaining signals stored on the current list 150 are not executed at that point.
    In step 9 (4) -2, the instruction processor 122 checks whether the flag SP_interrupt is set. The SP_interrupt can be set in step 8 (4) -7 when an externally generated signal has the highest level priority and the currently executing job is done or a timeout occurs (action A (SP 3), step 8 (3) -2)]. If the determination is final in step 9 (4) -2, steps 9 (4) -7 to 9 (4) -9 are executed before the end of action A (IP) 4.
    In step 9 (4) -7, the instruction processor 122 sets the state to the idle state. Then, for each job stored in the current list 150, the command processor 122 sends a signal to the signal processor 124 (the signal processor from the current list 150 in [first to last order]). 124 to move the work effectively). The movement of each signal from the current list 150 is shown by signal processor 124 as event E (SP) 2 (see FIG. 6 and action A (SP) 2). In step 9 (4) -9, command processor 122 sends an exit signal to signal processor 124, which exit signal is viewed as event E (SP) 1 and is processed by signal processor 124. Respond to action A (SP) 1.
    If the checks in steps 9 (4) -1 and 9 (4) -2 are negative, then in step 9 (4) -1-3, the command processor 122 does not allow the current list 150 to be empty. Decide if In step 9 (4) -10 the instruction processor 122 fetches the signal associated with the first task in the current list 150 and starts executing the first task. After step 9 (4) -10, action A (IP) 4 ends as indicated by symbol 9 (4) -5.
    If none of the existing steps 9 (4) -1, 9 (4) -2, or 9 (4) -3 is deterministic, then at step 9 (4) -4 the instruction processor 122 The state is set to the idle state and an exit signal is sent to the signal processor 124 to indicate that there are no more jobs waiting to be executed in the current list 150. The exit signal is viewed by the signal processor 124 as an event E (SP) 1 and is responded by the signal processor 124 to the action A (SP) 1. After step 9 (4) -4, action A (IP) 4 ends as indicated by symbol 9 (4) -5.
    Execution is understood from the foregoing description that the looping operation can continue in the appropriate instance as the buffered signal in the current list 150 is executed until all tasks in the current list 150 have been executed.
    (9) IP receiving signal from SP to list current
    As mentioned above, the command processor 122 may receive a signal from the signal processor 124 that is put in the current list 150. Such may be the action A (SP) 1 (eg, steps 8 (1) -8, and 8 (1) -18, and 8 (1) -20) and A (SP) 4 [eg, step 8 (4) -9] specifically generates the performance by the signal processor 124 and is viewed by the command processor 122 as event E (IP) 9. In response to event E (IP) 9, command processor 122 performs action A (IP) 9, which is only a posting of the signal as the last signal on current list 150, as shown in FIG. 9 (9) (step 9 (9) -1).
    (10) IP receiving kill signal from SP
    As indicated previously, the "kill" signal may be generated by the signal processor 124 as it occurs during (e.g.) a time period expiration (action A (SP) 3, e.g., step 8 (3)). -10). Such a kill signal is seen by command processor 122 as event E (IP) 3 and responds to action A (IP) 3 as shown in FIG. 9 (3). Upon receipt of the kill signal, the instruction processor 122 sets the state to the idle state in step 9 (3) -1. Then, as a result of the time period expiration (e.g., timeout), in step 9 (3) -2, the instruction processor 122 essentially discards the current thread. In step 9 (3) -3, the command processor 122 sends an exit signal to the signal processor 124. Such an exit signal is shown as event E (SP) 1 like signal processor 124 and responds to action A (SP) 1 in the manner previously discussed (see FIG. 8 (1)).
    (11) IP forced exit of the buffered signal
    When the application programmer needs to confirm that the exit really exists, a forced exit command of the buffered signal is issued. That is, a small delay must be inserted, so other threads have the potential to run. When no forced departure of the buffered signal occurs, command processor 122 generates event E (IP) 7 and responds to action A (IP) 7. Its step is depicted in Fig. 9 (7). In step 9 (7) -1, the command processor 122 sends a signal for each task remaining in the current list 150 to the signal processor 124, and sends the contents of the current list 150 to the signal processor 124. To move effectively. Thereafter, the instruction processor 122 sets the state to the idle state (step 9 (7) -2). The command processor 122 then sends an exit signal to the signal processor 124 in step 9 (7) -3. Such an exit signal is shown as event E (SP) 1 like signal processor 124 and responds to action A (SP) 1 in the manner previously discussed (see FIG. 8 (1)).
    Alternatively to the step shown in Fig. 9 (7), an action comparable to a forced exit may instead be performed by sending a signal with a time delay.
    5 illustrates another embodiment of the present invention, in particular a plurality of instruction processors in addition to signal processor 224, bus handler 230, and shared memory 227 (with both program storage and data storage). (222 1 , 222 2 ,..., 222 n ). Each command processor 222 of the embodiment of FIG. 5 has a configuration discussed above with reference to FIG. 4.
    A block executing in a multi-IP environment such as FIG. 5 must be able to handle several simultaneous executions within the block, but otherwise only one processor should be able to prove that it executes simultaneously in the block (eg, signal Some means of device or other thread that synchronizes). In a system 220 such as that shown in FIG. 5, it is possible to assign a block to only one of the command processors 222. In such a configuration, such an assigned command processor 222 can take part of its data in a particular fast memory, making it possible to execute certain tasks very efficiently. However, as a trade-off, the other instruction processor 222 must change the context.
    Therefore, it is seen from the foregoing description that the command processor of the present invention is included in the scheduling of a job executed by the command processor which basically enters a job associated with the buffered signal onto the current list 150 (e.g., As occurs in step 9 (11) -7 of action A (IP) 11 (see Fig. 9 (11)). If the buffered signal is to be generated just before exiting the currently executing job, except for the lowest priority level, and if no interrupt is set, then the job associated with the buffered signal is executed on exit from the job where the buffered signal is generated. (See step 9 (11) -6 of action A (IP) 11 in Fig. 9 (11)).
    Subsequently, when the command processor exits from the job executed as a result of the generation of the buffered signal, the command processor may take one of several alternative steps depending on the priority level of the buffered signal and which interrupt is set. Can be performed. The first alternative involves performing the same as obtaining the first (next) task from the current list (see step 9 (4) -10 of action A (IP) 4 in FIG. 9 (4)). The second alternative step includes in the signal processor 124 scheduling control that returns as occurs when the buffered signal is at the lowest priority level. The third alternative step involves moving the entire contents of the current list to the signal processor 124 as occurs when an interrupt occurs (step 9 (4) of action A (IP) 4 in FIG. 9 (4). ) -8].
    In connection with the first alternative, the continuous task on the current list may be executed continuously as the task on the current list exits. That is, when the fetched job from the current list 150 (as in step 9 (4) -10) completes, the exit instruction executes the next signal on the current list 150 according to the priority level and interrupt status. Create an (other) event E (IP) 4 that can be derived as:
    As is particularly understood from step 9 (11) -5 of Fig. 9 (11), whether or not the task associated with the buffered signal is executed immediately after the task of generating the buffered signal is determined by the type of command (e.g., Or exit command). Therefore, the instructions causing the generation of the buffered signal must be in a predetermined order within the job so that the instructions have a buffered signal that is executed immediately upon completion of the job. Otherwise, the task associated with the buffered signal remains on the current list 150 and continues to run on the task associated with the other buffered signal, or is moved to the signal processor 124.
    When job execution by the command processor is interrupted, the entire contents of the current list 150 are moved to the signal processor 124. The signal processor 124 puts the signal from the current list 150 into one of the buffers 142 according to the priority level of the shifted signal.
    In general, when the command processor needs a new signal for execution from the signal processor (as occurs when receiving an exit signal from the command processor), the signal is old (oldest) and priority level (i.e., level A, Fetched from the buffers 142A to 142B in accordance with B, C, or D (see action A (SP) 1 in Fig. 8 (1)). The flags "Activation_Priority" and CurrentThread_ID are set according to the priority level and thread ID of the fetched signal, and the fetched signal is sent to the command processor (steps 8 (1) -19 in Fig. 8 (1)). Reference]. In addition, the signal processor sends a job to the current list 150 in the buffers 142A-142B having the same thread ID as the fetched job (see steps 8 (1) -20 in FIG. 8 (1)), Jobs with the same thread ID can run in close proximity.
    Therefore, the signal processor 124 also has the ability to send a signal to the current list 150. This is especially true when the signal processor moves another signal from the at least one buffer with the same thread identification as the signal being moved to the command processor to the current list. The signal processor 124 is configured such that the thread ID of the externally generated signal (received via either the area processor bus handler 30 or the processor bus handler 31) is the CurrentThreadID processed by the command processor 122. A similar posting of the signal occurs on the current list 150 when determining that (see step A (SP) 4-5 in FIG. 8 (4)).
    As mentioned above, if the priority level of a fetched job is one of the "C" priority level or "D" priority level, the signal processor determines which jobs of similar priority level are currently interrupted, and if so, the interrupted job. While resuming execution, the fetched job is sent back to the appropriate one of the buffers 142C or 142D. See action A (SP) 1.
    If the command processor should execute a level D signal at a time of receiving a higher priority signal (e.g., from a command processor, from an area processor, or from another "command processor"), the level D signal by the command processor. The execution of is interrupted immediately. (See, for example, steps 8 (2) -7 in Fig. 8 (2) and steps 8 (4) -8 in Fig. 8 (4)).
    In another embodiment, command processor 122 is provided as a plurality of current lists 150A-150D, each one of the plurality of current lists being associated with a corresponding priority level. For example, a job with priority level "A" is placed in place on the current list 150A; A job with a "B" priority level is placed in place on the current list 150B; And so on.
    It should be understood that changes to the foregoing descriptions can be made, in particular, by examining the desired communication design. For example, with reference to event E (SP) 1 (receipt of the exit signal from command processor 122) and action A (SP) 1, a stable alternative procedure is performed. In one such example, while expecting an exit signal from command processor 122, signal processor 124 may go ahead and prepare a signal for command processor 122 in advance. Then, when command processor 122 comes to an exit point (from which to request information from signal processor 124), command processor 122 may check whether there is a ready message waiting for it. In such a procedure, the command processor 122 does not wait for the signal processor 124 in an exit situation.
    Advantageously, by providing features such as the current list 150, the central processing system according to the present invention can effectively use very fast memory (e.g. cache memory), because the central processing system of the present invention This is because the context does not change at a rate to negate the effect of fast memory. In particular, the command processor of the present invention may reuse "cached" data. That means that previously accessed data in the thread can be reused. In addition, by fetching data from basic memory (eg DRAM), buffers of one or more data words can be fetched at a time. Therefore, many major memory accesses can be performed as cache accesses, reducing the load on the instruction processor.
    Moreover, the central processing system in accordance with the present invention causes the signal processor 124 to mitigate some of its operations as the command processor 122 itself schedules from the current list 150 for jobs associated with buffered signals. In any normal traffic synthesis performance (with a 1 ms timeout), significant operational load reduction is realized for the signal processor 124.
    In addition, in the present invention, the buffered signals are often executed immediately when they occur, thereby reducing the transfer load with the signal processor 124, so that the instruction processor 122 reduces the operating load.
    In a system configured in accordance with the present invention, the clock frequency of the command processor 122 need not be limited by the clock frequency of the signal processor 124.
    The central processing system of the present invention handles the buffered signal schedule faster than the described prior art method. Although the number of primary memory accesses decreases in accordance with the present invention, the memory bandwidth increases because the instruction processor 122 fetches a larger block of data in each primary memory access.
    In accordance with the present invention, the signal processor takes a lot of time to prepare for the job since it takes more time between the fetching of the job from the job buffers 142A- 142D by the signal processor. Thus, the instruction processor stays idle for a shorter time when it leaves control to the signal processor to fetch the next thread.
    The present invention is particularly well suited for execution-intensive tasks that pass through switches based on, for example, CCITT No. 7 signaling, home location registers (HLRs), service control points (SCPs) that do not frequently interact with the region handler. To support such an application, the present invention advantageously provides thread IDS for externally generated signals (see step A (SP) 4-1 in FIG. 6A), so that jobs belonging to the same thread are executed as one thread. To increase the number of tasks executed between context switches.
    The present invention enables emulation of certain devices, such as a central processor of an Ericsson AXE 10 switch, in particular because the workstation is provided as a cache memory in a RISC workstation.
    However, it should be understood that the principles of the present invention do not necessarily require separate processors for the signal processor and command processor. In this regard, the present invention encompasses a single processor that emulates functions other than those described herein, both as signal processors and as command processors.
    While the invention has been particularly shown and described with reference to the preferred embodiments thereof, those skilled in the art can make various changes herein without departing from the spirit and scope of the invention.
    Table of Components (1410-13)
    Command Processor Unit (22) ... 3
    Signal processing unit (24) ..................................... 3
    Program storage (PS) (26) ......................... 3
    Data Storage (DRS) (28) ............. 3
    Multiple Zone Handler Bus Handlers (RPHs) (30 1, ... n ) ... 3
    "Other" handler bus handler (IPB) (31) ... 3
    Retention unit (MAU) (32) ........................ 3
    Buses (34 and 36) .....................
    Bus (39) ... 4
    Task Scheduler (40) ........................ 4
    Job Buffers (42A to 42D) ......................... 4
    Line (52) ... 5
    Line (54) ... 7
    Line (56) ... 8
    Line (58) ... 8
    Command Processor Unit (IP) (122) ... 13
    Signal Processing Unit (124) ... 13
    Program storage (PS) (126) ... 13
    Data Storage (DRS) (128) ... 13
    Multiple Zone Handler Bus Handlers (RPHs) (130 1, ... n ) ..... 13
    "Other" handler bus handler (IPB) (131) ......... 13
    Current list memory (150) ........................... 14
    Central Processing Unit (CPU) (160) ... 14
    RM (What Is It ) (162) ........................ 14
    Quick Memory (164) .....................
    Memory Access / Interface (166) ... 14
    Cache Memory (168A to 168C) ... 14
    Memory Card (170A-170G) ... 14
    Memory Bus (172) ... 17
    Line (154) ... 17
    Line (152) ... 22
    Central Processing System (220) ............. 23
    Signal Processor (224) ... 23
    Bus handler (230) ... 23
    Shared Memory (227) ... 23
    权利要求:
    Claims (41)
    [1" claim-type="Currently amended] A processing system for scheduling a job to be executed by a command processor and transmitting a signal associated with the job to the command processor when the command processor requests the next job for execution,
    The current list memory is maintained by the command processor, causing the current job executed by the command processor to cause the command processor to generate a buffered signal associated with the new job being executed, and the command processor is associated with the new job. And cause the buffered signal to be stored in the current list.
    [2" claim-type="Currently amended] 2. The processing system of claim 1, wherein the command processor selectively stores a buffered signal associated with a new task in the current list according to a priority level of the current task causing the buffered signal to be generated.
    [3" claim-type="Currently amended] 2. The processing system of claim 1, wherein the command processor selectively stores a buffered signal associated with the new task in the current list depending on whether the signal processor generates an interrupt in the command processor.
    [4" claim-type="Currently amended] 2. The processing system of claim 1, wherein the new job is executed immediately if the instructions in the current job that generate the buffered signal are in a predetermined order within the current job.
    [5" claim-type="Currently amended] 5. The processing system according to claim 4, wherein a new task is executed immediately if the instruction in the current task that generates the buffered signal immediately precedes the exit instruction of the current task.
    [6" claim-type="Currently amended] 2. The processing system of claim 1, wherein the command processor causes a buffered signal associated with the new job to be stored at a predetermined location in the current list.
    [7" claim-type="Currently amended] 7. The processing system of claim 6, wherein the command processor causes a buffered signal associated with the new job to be stored as the last job in the current list.
    [8" claim-type="Currently amended] 2. The processing system of claim 1, wherein the command processor finishes executing a task associated with the buffered signal, and the command processor sends an exit signal to the signal processor if the task associated with the buffered signal has a predetermined priority level. .
    [9" claim-type="Currently amended] 9. The processing system of claim 8, wherein the predetermined priority level is the lowest priority level.
    [10" claim-type="Currently amended] The method of claim 1, wherein the command processor finishes executing the task associated with the buffered signal, and when the signal processor generates an interrupt to the command processor, the command processor sends all remaining tasks in the current list to the signal processor. Processing system.
    [11" claim-type="Currently amended] 2. The processing system of claim 1, wherein the command processor finishes executing the job associated with the buffered signal, and the command processor fetches and executes additional jobs from the current list.
    [12" claim-type="Currently amended] The method of claim 1, wherein the command processor finishes executing the task associated with the buffered signal, and the command processor then:
    (A) sending an exit signal to the signal processor if the task associated with the buffered signal has a predetermined priority level;
    (B) if the signal processor issues an interrupt to the command processor, send all remaining work in the current list to the signal processor;
    (C) optionally, one of fetching and executing additional tasks into the current list.
    [13" claim-type="Currently amended] 2. The processing system of claim 1, wherein the signal processor is emulated by a command processor that performs tasks scheduled by the signal processor.
    [14" claim-type="Currently amended] 2. The processing system of claim 1, wherein the signal processor selectively stores signals on a current list.
    [15" claim-type="Currently amended] 15. The processor of claim 14, wherein the signal processor has at least one buffer in which signals are fetched and passed to the command processor, and when the signal processor passes the signal to the command processor, the signal processor identifies a thread, such as a signal that is moved to the command processor. And move another signal from the at least one buffer to the current list.
    [16" claim-type="Currently amended] 2. The processing system of claim 1, wherein a plurality of current list memories are maintained by an instruction processor.
    [17" claim-type="Currently amended] 17. The processing system of claim 16, wherein each of a plurality of current list memories is associated with a corresponding priority level.
    [18" claim-type="Currently amended] The signal processor schedules the task to be executed by the command processor, and when the command processor executes the task, it passes signals associated with the task to the command processor, and the signal processor is operable to receive externally generated signals from the command processor without the processing system. In the processing system which can
    When receiving a signal from the command processor or externally without a processing system, the command processor receives a signal whose priority level is the highest priority level and exceeds the priority level of the current job executed by the command processor. And a signal processor for setting interrupts.
    [19" claim-type="Currently amended] 19. The command processor of claim 18, wherein the current list memory is maintained by the command processor and when the current job executed by the command processor causes the command processor to generate a buffered signal associated with the new job being executed. Causes the buffered signals associated with the new job to be stored in the current list, and the priority level of the externally generated signal is the highest priority level and exceeds the priority level of the current job executed by the command processor. When the contents of the current list are moved to the signal processor.
    [20" claim-type="Currently amended] 19. The signal processor of claim 18, wherein the signal processor is executed by the command processor when the current job executed by the command processor has a lowest priority and the externally generated signal has a higher priority level than the lowest level priority. A processing system for interrupting a job.
    [21" claim-type="Currently amended] 19. The processing system of claim 18, wherein the signal processor is emulated by a command processor that performs tasks scheduled by the signal processor.
    [22" claim-type="Currently amended] A method of operating a processing system in which a signal processor schedules a task to be executed by a command processor and delivers a signal associated with the task to the command processor when the command processor executes a task scheduled by the signal processor, the method comprising:
    The current job executed by the command processor causes the command processor to generate a buffered signal associated with the new job being executed, and the command processor causes the buffered signal associated with the new job to be stored in the current list, And a command processor for maintaining a current list.
    [23" claim-type="Currently amended] 23. The operation of a processing system of claim 22, wherein the command processor selectively stores a buffered signal associated with a new task in the current list according to a priority level of the current task causing the buffered signal to be generated. Way.
    [24" claim-type="Currently amended] 23. The method of claim 22, wherein the command processor selectively stores a buffered signal associated with the new task in the current list depending on whether the signal processor generates an interrupt in the command processor.
    [25" claim-type="Currently amended] 23. The method of claim 22, wherein if a command in the current job that generates the buffered signal is in a predetermined order within the current job, the new job is executed immediately.
    [26" claim-type="Currently amended] 24. The method of claim 23, wherein the new task is executed immediately if the instruction in the current task that generates the buffered signal immediately precedes the exit instruction of the current task.
    [27" claim-type="Currently amended] 23. The method of claim 22, wherein the command processor causes a buffered signal associated with the new task to be stored at a predetermined location in the current list.
    [28" claim-type="Currently amended] 28. The method of claim 27, wherein the command processor causes a buffered signal associated with the new task to be stored as the last task in the current list.
    [29" claim-type="Currently amended] 23. The processing system of claim 22, wherein the command processor finishes executing the task associated with the buffered signal, and the command processor sends an exit signal to the signal processor if the task associated with the buffered signal has a predetermined priority level. How to operate.
    [30" claim-type="Currently amended] 30. The method of claim 29, wherein the predetermined priority level is the lowest priority level.
    [31" claim-type="Currently amended] 23. The method of claim 22, wherein the command processor finishes executing the task associated with the buffered signal, and when the signal processor issues an interrupt to the command processor, the command processor sends all remaining tasks in the current list to the signal processor. Method of operation of processing system.
    [32" claim-type="Currently amended] 23. The method of claim 22, wherein the instruction processor finishes executing the task associated with the buffered signal, and the instruction processor fetches and executes additional tasks from the current list.
    [33" claim-type="Currently amended] 23. The method of claim 22, wherein the command processor finishes executing the task associated with the buffered signal, the command processor then:
    (A) sending an exit signal to the signal processor if the job associated with the buffered signal has a predetermined priority level;
    (B) when the signal processor issues an interrupt to the command processor, sending all remaining work in the current list to the signal processor;
    (C) optionally performing one of the steps of fetching and executing additional tasks into the current list.
    [34" claim-type="Currently amended] 23. The method of claim 22, wherein the signal processor is emulated by a command processor that performs tasks scheduled by the signal processor.
    [35" claim-type="Currently amended] 23. The method of claim 22, wherein the signal processor selectively stores signals on a current list.
    [36" claim-type="Currently amended] 34. The processor of claim 33, wherein the signal processor has at least one buffer in which signals are fetched and passed to the command processor, and when the signal processor passes the signal to the command processor, the signal processor identifies a thread, such as a signal that is moved to the command processor. And moving another signal from the at least one buffer to the current list.
    [37" claim-type="Currently amended] 23. The method of claim 22, wherein a plurality of current list memories are maintained by an instruction processor.
    [38" claim-type="Currently amended] 23. The method of claim 22, wherein each of a plurality of current list memories is associated with a corresponding priority level.
    [39" claim-type="Currently amended] The signal processor schedules the job to be executed by the command processor, and when the command processor executes the job, it passes signals associated with the job to the command processor, and the processing system is operable to receive externally generated signals from the command processor without the processing system. In the operation method of the processing system,
    When receiving a signal externally from the command processor or without a processing system, the priority level of the externally generated signal is the highest priority level and exceeds the priority level of the current job executed by the command processor. And a signal processor for setting interrupts in the command processor.
    [40" claim-type="Currently amended] 40. The command processor of claim 39 wherein the command processor maintains a current list memory and causes the current job executed by the command processor to cause the command processor to generate a buffered signal associated with a new job executed. The buffered signals associated with the new job are stored in the current list, and the priority level of the externally generated signal is the highest priority level and exceeds the priority level of the current job executed by the command processor. When the contents of the current list are moved to the signal processor.
    [41" claim-type="Currently amended] 40. The signal processor of claim 39, wherein the signal processor is executed by the command processor when the current job executed by the command processor has a lowest priority and the externally generated signal has a priority level that is higher than the lowest level priority. A method of operating a processing system comprising interrupting a job.
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    同族专利:
    公开号 | 公开日
    AU1218897A|1997-07-14|
    AU714853B2|2000-01-13|
    WO1997022927A1|1997-06-26|
    CA2240778A1|1997-06-26|
    EP0868690A1|1998-10-07|
    CN1209207A|1999-02-24|
    JP2000502202A|2000-02-22|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1995-12-19|Priority to US57497795A
    1995-12-19|Priority to US8/574,977
    1996-12-19|Application filed by 에를링 블로메, 타게 뢰브그렌, 텔레폰아크티에볼라게트 엘엠 에릭슨
    1996-12-19|Priority to PCT/SE1996/001706
    2000-11-06|Publication of KR20000064491A
    优先权:
    申请号 | 申请日 | 专利标题
    US57497795A| true| 1995-12-19|1995-12-19|
    US8/574,977|1995-12-19|
    PCT/SE1996/001706|WO1997022927A1|1995-12-19|1996-12-19|Job scheduling for instruction processor|
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